A drift-diffusion/Monte Carlo simulation methodology for Si/sub 1-x/Ge/sub x/ HBT design

An accurate and efficient simulation methodology for Si/sub 1-x/Ge/sub x/ HBTs is presented. A two-dimensional (2-D) drift-diffusion solver is employed for dc and ac characteristics, and one-dimensional (1-D) full-band Monte Carlo for transport in the base-collector high-electric-field region. Extrinsic parasitics are introduced as lumped circuit elements whose values are obtained from measurements and layout considerations. This approach not only reduces the computational cost of the simulation, but it also helps to differentiate the relevance of the intrinsic and extrinsic device parameters. We discuss the calibration of the simulation on a 0.25 /spl mu/m process and use a 1-D regional analysis in the quasi-static approximation to identify the major source of delay. Results of the delay analysis were used to improve device performance for the 0.16 /spl mu/m technology node.