Prediction of Register Instance Usage and Time-sharing Register for Extended Register Reuse Scheme.

Register renaming is the key for the performance of out-of-order processors. However, the release mechanism of the physical register may cause a waste from time dimension. The register reuse technique is the earliest solution to release a physical register at renaming stage, which takes the advantage of those register instances with only one time use. However, the range of possible reuse mined by this scheme is not high, and the physical structure of the register have to be modified. Aiming at these two problems, we propose an extended register reuse scheme. Our work presents: 1) prediction of the use times of the register instance, so as to reuse the physical registers at the end of the last use, to expand the range of possible reuse. 2) A design of time-sharing register file with little overheads which is implemented by Backup Registers, avoiding to modify the physical register structure. Compared with the original register reuse technique, this work achieves 8.5% performance improvement, alternatively, 9.6% decrease of the number of physical registers with minor hardware overhead.