Inverse lithography (ILT) mask manufacturability for full-chip Device
2009
Inverse Lithography Technology (ILT) is becoming one of the strong candidates for 32nm and below. ILT masks
provide significantly better litho performance and need to be enabled for production as one of the leading candidates for
low-k1 lithography. By the very nature ILT masks are computed, they could seem to be complicated to manufacture in
production. In a prior publication [1], it has been shown at clip level that the Inverse Synthesizer (IS TM ) product has the
capability to adjust for mask complexity to make it more manufacturable while maintaining the significant litho gains of
nearly ideal ILT mask. The production readiness of ILT needs to be studied at full chip level with various aspects
including mask data fracturing, MRC constraints, writing time, and inspection.
The computation of ILT mask usually starts with the calculation of an optimized contoured mask then followed by
manhattanization step to convert contour into horizontal-vertical segments. By varying the segmentation length during
manhattanization, it can affectively change the mask complexity while maintains the shape of mask. The result of
segmentation length impact on writing time and lithography performance at full-chip is presented. MRC is another
important factor in mask manufacturability which needs to be carefully studied. Mask pattern transfer fidelity and
inspectability at various selected MRC rules are also presented in the paper.
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