Design Strategies for Ultralow Power 10nm FinFETs

Abstract In this work, new design strategies for 10 nm node NMOS bulk FinFET transistors are investigated to meet low power (LP) (20 pA/μm  OFF OFF OFF ), transconductance ( g m ), gate capacitance (C gg ) and intrinsic frequency ( f T ). It is shown that the gate length of 20 nm for the 10 nm node FinFET can meet the requirements of LP transistors and ULP transistors by source-drain extension engineering, punch-through stop doping concentration, and choice of gate workfunction.