Parallel Robust Absolute Orientation on FPGA for Vision and Robotics

The performance of absolute orientation, a computationally intensive process, plays a key role in a plethora of computer vision and robotics applications. This paper focuses on accelerating the execution of a robust algorithm based on Horn's quaternion solution and presents a HW architecture as well as its FPGA implementation. The proposed design approach relies on the specifics of the algorithm to develop each of its architectural parts by using either low-level Hardware Description Language (HDL) or High Level Synthesis (HLS) descriptions, significantly improving both the design and the time required for development. Combining HDL and HLS described parts leads to an architecture design that exploits parallelism, improves HW utilization and enhances the efficiency of calculations by customizing complicated arithmetic operations. Our implementations on Kintex 7 XC7K325T achieve 61x total speedup versus conventional SW on an embedded processor.