New DfM Domain: Stress Effects

The mismatch of thermal properties among the IC component materials results in thermo-mechanical stress inside and around the devices [1–3]. It is tempting to divide the sources of such stress into the intentional and non-intentional ones or intrinsic and extrinsic. However, a better distinction would be whether we are able to take advantage of them in product implementation (intrinsic) or are they outside the device model space (extrinsic). When dividing them by the source of stress, one may identify the ones at die level, i.e., built into silicon, and the ones at package level, i.e., between the chip and its package. (Chip-Package Integration CPI). A DfM methodology for controlling stress, using design rules and material properties for both chip and package stack design, is required to span orders of magnitude of physical dimensions. It should not only comprehend the effects of mechanical stresses in electrical responses of the circuits, but also their reliability impact.