Gating internal nodes to reduce power during scan shift

It is a common practice to gate a limited number of scan cells in order to reduce overall switching activity during shift, thereby, reducing the circuit's dynamic power consumption. In this paper, we propose a novel approach to reduce overall shift power during test by inserting extra hardware at the output of scan cells and internal gates. Based on the estimated dynamic power (using PrimeTime-PX), the proposed approach uses a linear time algorithm to identify the nodes to be gated. To avoid degrading the timing of the circuit, additional logic is added only at paths that are not timing-critical. The proposed approach significantly outperforms all approaches that gate only scan cells. Experimental results on ISCAS and ITC benchmarks show that on average more than 48% of the dynamic power can be reduced while reducing the hardware overhead by up to 3.75X.