Diode array architecture for addressing resistance memory arrays at the nanoscale

Memory structure comprising: a first conductor (BL); a second conductor (WL); a resistive memory cell (130) is connected to the second conductor (WL); a first diode (134) connected to the resistive memory cell (130) and the first conductor (BL) is connected and in the forward direction from the resistive memory cell (130) to the first conductor (BL) is oriented; and a second diode (132) connected to the resistive memory cell (130) and the first conductor (BL) and connected in parallel with the first diode (134) and in the reverse direction from the resistive memory cell (130) to the first conductor (BL) is oriented ,