A monolithic charge multiplexer with 0.5% accuracy

Abstract This paper describes a 16 channel monolithic charge multiplexer providing a close tolerance, low cost, low power solution to the problem of handling the signals from detectors with large numbers of channels. Outputs may be wire-orred to increase the degree of multiplexing. A system designed with this chip and with suitably close tolerance processing downstream will have a gain match of ±0.5% and a front end chip cost of approximately $1 per channel. The chip is fabricated in CMOS technology and the test of a 1500 channel system has demonstrated the feasibility of CMOS in this context. The chip produceds a prompt sum of the charges from the 16 signal sources and integrates and stores the individual charges for later serial readout. A single network provides amplifier bias and releases area to facilitate optimum noise performance and signal handling. Amplifier and bias network design together with p-well screens to isolate storage capacitors from the substrate provide the power line rejection essential in systems generating a trigger from large numbers of channels.