A petri-net based Pre-runtime scheduler for dynamically self-reconfiguration of FPGAs (abstract only)

Dynamically Reconfigurable Systems (DRS) offer a very interesting alternative for embedded digital systems design. Tasks scheduling within a reconfigurable environment allows the development of systems with better execution performance, chip area economy and lower power consumption. This paper describes a Petri Net based methodology for the design of dynamically reconfigurable systems, where tasks scheduling has as prime objective the best temporal performance of the overall application. The methodology includes the generation of an embedded controller supporting the scheduling process in the target architecture.