40 and 60 GHz frequency doublers in 90-nm CMOS

The design and characterization of both a 40 GHz and a 60 GHz frequency doublers in 90-nm CMOS technology is presented. Conversion loss of 15.8 dB at 40 GHz output frequency with 3 dBm input power and 15.3 dB at 60 GHz with 5 dBm input power was achieved for the two frequency doublers. The power consumption was about 4 mW for both designs.