Low-k spacers for advanced low power CMOS devices with reduced parasitic capacitances

Integration of low-dielectric constant SiCOH dielectrics (k~3) adjacent to gate stacks is demonstrated using 65 nm technology. Substantial reductions in parasitic capacitances are achieved through reductions in the outer fringe component of the overlap capacitance and the capacitance between the gate stack and metal contacts. These results are consistent with modeling. Although this is demonstrated with 65 nm devices, low-k spacers can cut active power consumption and have the potential to improve performance through reductions in parasitic capacitances which will be of greater importance for future technology nodes.