Mapping system-on-chip designs from 2-D to 3-D ICs

System-on-chip (SoC) designs suffer from the growing global interconnect delay as device density and chip area increase. Three-dimensional integrated circuits (3D ICs) have been proposed as a way to reduce global wire length. Despite this key advantage of 3D ICs, 3D designs must effectively address two critical issues: heat dissipation and manufacturing cost. In this paper, we propose a new methodology that explores the trade-off between performance and cost of a SoC design, while keeping maximum on-chip temperature at an acceptable level. We analyze the performance of two multimedia systems and describe the implications of scaling SoC designs to 3D.