Experimental and Numerical Investigation Into the Influence of Chip-on-Film Package on Component Operating Temperature in Natural Convection

The thermal issues of chip-on-film (COF) packages are becoming increasingly important for high-pin-count chips, whose performance is becoming increasingly limited by the maximum power that can be spread without exceeding the maximum junction temperature. This paper conducts an experimental investigation to investigate the relationship between power dissipation and the surface temperature of the thermal chip in COF applications. This paper develops an ANSYS finite-element (FE) model to simulate the junction temperature and temperature distribution within the COF package under various boundary conditions. Based on an effective methodology of equivalent models for thermal conductance, comparing the simulation results with the experimental temperature measurements confirms the validity of the numerical model. This paper uses the proposed model in a $\hbox{2}^{3}$ factorial design process to evaluate the effect of the major components of COF packages. Results show that the thickness of copper lead plays a significant role in efficient thermal power dissipation of the package due to its inherent advantage. Several parametric studies reveal the effects of various configurations of the thermal model and the effects of the voids. This paper also analyzes the thermal resistance at the junction of the package. Results show that the natural convection of the COF package with thermally conductive tape achieves a cooling function that keeps the junction temperature of the COF package under 85 $^{\circ}\hbox{C}$ without using a fan. The validated FE models in this paper have enormous potential to quickly assess the thermal limits of many future COF packages and their variations.