A Network Security Processor Design Based o na nIntegrate dSO CDesig nan dTes tPlatform

In this paper we present a generic Network Security Processor (NSP) design suitable for a wide range of security related protocols in wired or wireless network applications. Following the platform-based design methodology, we develop four specific platforms, i.e., architecture platform, EDA platform, Design-for-Testability (DFT) platform, and prototyping platform, for our NSP design. With these platforms, design of the NSP chip becomes more efficient and systematic. A prototype chip of the NSP has been implemented and fabricated with a 0.18µm CMOS technology. The chip area is 5mm×5mm (with 1M gates approximately), including I/O pads. The operating clock rate is 80MHz. The best performance of the crypto-engines is 1.025Gbps for AES, 1.652Mbps for RSA, 125.9/157.65Mbps for HMACSHA1/MD5, and 2.56Gbps for random number generator. Comparison result shows that our NSP is efficient in terms of performance, flexibility and scalability.