Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn + implant and SiC S/D for nFETs by C + implant

We report, for the first time, a simple and cost effective co-integration of strained p and n-FETs using tin (Sn) and mono-carbon (C) implant in Source/Drain (S/D) of p- and n-FETs, respectively, to induce beneficial strain. For the first time, a single laser anneal step was employed to substitutionally incorporate the Sn and C atoms simultaneously into lattice sites. 7 at.% substitutional Sn concentration (the equivalent of adding 35% Ge to SiGe S/D stressors) was achieved in the Si 0.7 Ge 0.3 S/D of Si channel p-FET. A significant enhancement of up to 150% in hole mobility and 71% in drive current for a 50 nm gate length device was observed. Mono C implanted S/D n-FETs show 19% current drive increase. With the simultaneous integration of Ni based FUSI gate, we provide a highly useful extension to future S/D technology for further I D,sat and mobility improvement.