Dedicated technology threshold voltage tuning for 6T SRAM beyond N7

As scaling continues for FinFET technology nodes, variability in combination with targeted lower supply voltages results in reduced SRAM stability margins. In this paper, threshold voltage tuning from the technological side is used to enable low SRAM Vmin with minimum impact on logic performance. Furthermore, lower overall system energy consumption can be achieved by the lower Vmin. This exercise is crucial for the enablement of future technology nodes where single V TH masks could become a necessity.