BTI Characterization of MBE Si-Capped Ge Gate Stack and Defect Reduction via Forming Gas Annealing.

The capacitance-voltage (C-V) hystereses under positive and negative stress fields were studied on molecular beam epitaxy (MBE) Si-capped Ge metal-oxide-semiconductor (MOS) capacitors to investigate pre-existing and generated shallow and deep oxide traps. Post metallization forming gas annealing (FGA) has reduced the effective oxide trap density ( $\Delta$ N eff ) of one order of magnitude, achieving values lower than the one required of sufficient reliability (target $\Delta$ N eff ~3×1010 cm−2) at an effective oxide fields (E ox ) of ~10MV/cm (i.e., larger than at operating condition). This result demonstrates the effectiveness of FGA in reducing the hole traps in the gate stack. Furthermore, the measured C-V hystereses and the stress-induced-leakage-current (SILC) under long-time stress remained extremely small, showing the superior reliability of the MBE Si-capped Ge gate stacks on Ge.