Device performance analysis on 20nm technology thin wafers in a 3D package

This paper presents the impact of wafer thinning process on GLOBALFOUNDRIES high-k metal gate CMOS wafers with TSV. The initial study of wafer backside surface finish and thickness was performed on non-TSV wafers, and the impact on active devices such as: MOS (metal-oxide semiconductor) capacitors, ring oscillators, analog circuit performance and front end of line (FEOL) reliability macros was characterized. Based on the experimental results, a suitable wafer surface finish and thickness was selected for TSV wafer processing. The impact of wafer thinning on device performance was monitored at various stages of packaging, including before thinning, after thinning, end-of line (EOL), and post package reliability tests.