A Continuous-Adaptive DDR2 Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test

An experimental chip for a 32b wide DDR2 SDRAM interface for SoC is fabricated in a 90nm CMOS process and achieves 960Mb/s/pin operation. Impedance-calibration circuits and flexible round-trip circuits in a continuous-adaptive DDR2 interface are used to suppress skew and allow a longer round-trip time.