High-Level soc modeling and performance estimation applied to a multi-core implementation of LTE enodeb physical layer

The impressive technical and technological advances in both fields of semi-conductors and software engineering enabled modern System-on-Chip "SoC" to host complex and interdependent applications. These advances are coupled with higher systems complexity and heterogeneity. Thus, forcing designers to re-evaluate their design methodologies and to raise the level of abstraction to the system level targeting the co-design of the entire SoC rather than just individual components. The objective of this Thesis work is to provide the system designer with means (on the methodology and tools levels) to estimate system's performances and evaluate rapidly and very early the design decisions in the SoC design flow. Our work provides contributions in two main aspects: (1) On the conceptual Level, we defined (using the UML meta-modeling concepts) modeling concepts to estimate shared resources impact on system's overall performances, by introducing the "virtual node" concept for scheduling and shared resources access control. Furthermore, we introduced the "Communication Pattern" concept for modeling the interaction between architecture elements to ensure the orthogonalization of computation and communication concerns. (2) On the Simulation Level: A SystemC simulator was written to simulate the UML models. Simulation is done at a high level of abstraction and runs faster than real time execution. The usability and capabilities of our approach are shown with an industrial use case. We modeled a Freescale multi-core DSP platform for LTE base stations (LTE stands for Long Term evolution is the 4G standard for cellular networks). The comparison of modeling results with the real implementation proved the accuracy of our approach. Key themes: System level design and modeling, UML for embedded systems, Resources management and sharing, Communication modeling, Performance estimation, Telecommunication systems