Reliability assessment of microvias in HDI printed circuit boards

Accelerating adoption of CSP and flip-chip area array packaging for high performance and hand-held applications is the main driving force for high-density substrates and printed circuit boards. At the Packaging Research Center, Georgia Institute of Technology (PRC-GT), ultra-fine line high density interconnect (HDI) substrate technology is being developed as part of the system-on-a-package (SOP) research and testbed efforts to meet these emerging requirements. To be adopted by industry, this novel technology must demonstrate the critical elements of high reliability and low cost processing. The HDI and microvias structures discussed in this paper were fabricated on high Tg organic substrates using a sequential build-up process, and were subject to extensive liquid to liquid thermal shock testing. All 75 /spl mu/m microvias and above successfully passed 2000 cycles without failure, and first failure occurred at 1000 cycles for 50 /spl mu/m microvias on a 50 /spl mu/m thick dielectric layer. Microvia down to 25 /spl mu/m diameter on a 25 /spl mu/m thick dielectric layer have passed 2000 cycles with zero failures. Cross-sectioning confirmed that failures were caused by process related defects, such as thin electrolytic copper plating. This paper will discuss the reliability results of the PRC HDI microvias process and methods to improve the mechanical reliability of small photo defined microvias fabricated on similar laminate substrates.