Effects of Metal–Interlayer–Semiconductor Source/Drain Contact Structure on n-Type Germanium Junctionless FinFETs

In this paper, the effects of a metal–interlayer–semiconductor (MIS) source/drain (S/D) structure with a heavily doped interlayer on enhancement-mode n-type germanium (Ge) junctionless FinFETs (JLFETs) are demonstrated via 3-D technology computer aided design simulation. N-type Ge JLFETs using metal–semiconductor (MS) S/D structures face difficulty in operating in the enhancement mode, as severe Fermi-level pinning (FLP) triggers extremely high off-state current ( ${I}_{ \mathrm{OFF}}$ ) and extremely low on-state current ( ${I}_{ \mathrm{ON}}$ ). The MIS S/D structure can solve these problems by mitigating FLP. In the simulation of an n-type Ge JLFET with the MIS S/D structure, ${I}_{ \mathrm{OFF}}$ of $9.42 \times 10^{-10}$ A/ $\mu \text{m}$ , ${I}_{ \mathrm{ON}}$ of $6.09 \times 10^{{-4}}$ A/ $\mu \text{m}$ , and subthreshold slope of 65.38 mV/dec are achieved. The performance of the device for different channel-doping concentrations and fin dimensions is also evaluated. Thus, an MIS S/D structure with a heavily doped interlayer can effectively strengthen the performances of n-type Ge JLFETs beyond the sub-7-nm technology node.