Influence of lucky defect distributions on early TDDB failures in SiC power MOSFETs

In this work, we explore the effect of different defect profiles on the occurrence of early time-dependent-dielectric-breakdown (TDDB) to forecast the defect profile present in commercial grade SiC/SiO 2 DMOSFETs. Early failure simulations are performed using the recently developed “lucky defect” model. The model shows that the bulk defects in the gate oxide are the likely culprit for early TDDB failures through an increase in tunneling current via trap-assisted-tunneling (TAT). We show that an exponential distribution of “lucky defects” in the oxide bulk affects the failure distribution in a similar fashion to what we observe experimentally. We also identify the implications of under-sampling the population in these extrinsically dominated failure distributions. Armed with these tools, we show that, the speculated carbon rich transition layer at or near the interface is not likely present in the measured DMOSFETs.