A network flow approach for simultaneous escape routing in PCB

Simultaneous Escape Routing (SER) is one of the most difficult problems in the Printed Circuit Boards (PCBs) routing as the pins from inside of two ICs have to be escaped to the boundaries simultaneously. The ever evolving integrated circuits (ICs) manufacturing techniques have made SER even more difficult by increasing the complexity of these ICs to a whole new level. This increase in complexity of ICs has not only increased the number of pins in an IC but has also reduced the size of the package making SER in PCBs a very hectic task. The SER problem has not been addressed by many studies in the literature and mostly, heuristic algorithms have been proposed in order to solve SER problem which fail to achieve 100 percent route-ability. In this work, we employed network flow approach to solve the SER problem using optimization modeling technique. We propose two optimal algorithms that use integer linear program for testing different sizes of grids to check their efficiency. The analysis and results show the improved efficiency of the proposed algorithms in terms of route-ability, time consumption, independence from grid topology & component pin arrangement.