Advances in flash memory devices

Fundamental challenges are discussed concerning the down-scaling of flash memory cells for mass storage applications. A general scaling issue for all various memory cell concepts is the structuring limit of conventional lithography. Therefore sub-lithographical structuring methods like e.g., double-patterning for future flash chips, have been evaluated. Another common scaling challenge of charge trapping (CT) and floating gate (FG) cells, the two future concurrent flash memory cell concepts, is the introduction of new materials such as high k dielectrics. Their implementation into CT and FG cells and the scaling related electrical issues of both cell concepts is also been discussed.