Asynchronous circuits for dynamic voltage scaling

We have presented the appropriateness of the QDI (and pseudo-QDI) asynchronous -logic design approach to realize circuits and systems suitable for full -range DVS (from the nominal voltage near- V t voltage sub- V t voltage regions). Both block -level and gate -level pipeline structures have been presented. Using the block -level pipeline structure, we have presented an SSAVS system embodying block -level QDI asynchronous pipelines for a WSN with the objective of lowest possible power operation for the prevailing throughput and circuit conditions-V DD adjusted to within 50 mV of the minimum voltage, yet high operational robustness with minimal overheads. High robustness has been achieved by adopting the asynchronous QDI protocols, and the embodiment of our proposed PCSL. A reduced -overhead design has further been shown by adopting the asynchronous pseudo-QDI protocols, and the embodiment of PCSL. Using the gate -level pipeline structure, we have presented our proposed SABB cell design approach and evaluated an asynchronous QDI KS pipeline adder embodying SABB for full -range DVS operation. In summary, we show that QDI (and pseudo-QDI) asynchronous -logic, coupled with either PCSL or SABB cell design approaches, provides a low-cost high -reliability solution for circuits and systems exclusively designed for error free DVS.