Dielectric defects controlling instability in InGaAs n-MOSFETs with Al 2 O 3 /ZrO 2 gate stack

Instability under positive bias stress (DC and AC) in InGaAs channel nMOSFETs with a a 1nmAl 2 O 3 /5nmZrO 2 gate stack is studied. It is determined that the threshold voltage shift (ΔV T ) during stress is primarily caused by a recoverable electron trapping at pre-existing defects, which are located pre-dominantly in the Al 2 O 3 interfacial layer (IL). Generation of new electron trapping defects is found to occur in the IL, in the region close to the substrate, while trap generation in the high-k dielectric is negligible. The ΔV T recovery impacts the degradation dependency on the stress duty cycle and frequency.