Low-Power and Area-Efficient Shift Register Using Pulsed Latches with modified SSASPL with130nM CMOS Technology

This paper proposes a low-power and area-efficient shift register by using pulsed latches. The area and power consumption are reduced by replacing SSASPL (Static differential Sense Amp Shared Pulse Latch) to modified SSASPL. This method solves the timing problem between pulsed latches by replacing the usage of the conventional single pulsed clock signal to multiple non-overlap delayed pulsed clock signals. The shift register uses a small number of the pulsed clock signals by grouping the latches to N(N=4) sub shifter registers by using additional temporary storage latches. From the experiments and the results obtained it is observed that the proposed shift register is having less area and low power for an N-bit shift register. The design is implemented with 130nm technology in Tanner EDA (Electronic Design Automation) Tool.  With Vdd =1.8V, Freq=200MHz.