Thickness dependence of gate dielectric layer on structural and electrical characteristics in the pentacene thin-film transistors

We report on the fabrication of low-voltage pentacene thin-film transistors (TFTs) with CeO 2 -SiO 2 composite dielectric layers in the thickness range of 20 to 300 nm. The maximum field effect mobility of 0.97 cm 2 /V s and on/off current ratio of 10 4 were achieved under a low operating voltage of -2 V from our pentacene TFTs with 50 nm thin CeO 2 -SiO 2 composite dielectric layer. The capacitance and surface smoothness of the dielectric layer were improved with lowering the dielectric thickness. Pentacene TFTs with thin dielectric layers were thus found to be generally superior to the others with thick dielectric layers in device performance although the dielectric also showed its own thickness limit in enduring the 2 V gate bias. We conclude that there is an optimum dielectric thickness for the most desirable device performance and that our TFTs with the 50 nm thin gate dielectric have demonstrated the performance.