Silicon photonic integrated circuit for co-packaging with switch ASIC

Data center IP traffic is doubling every 2.5 years, driving the need to scale connectivity bandwidth on a similar cadence. At higher data rates the electrical link reach shrinks but energy efficiency does not improve significantly. Co-packaging optics close to ASICs enables data throughput scaling by reducing the SERDES power and hence overall power due to shorter electrical channels. Despite the advantages, co-packaging optics next to electronics can be challenging. This paper reviews Intel’s advancements in demonstrating industry’s first fully operational Silicon Photonic integrated circuit co-packaged with switch ASICs, describing in detail component level, integrated photonic integrated circuit (PIC) level, and transceiver module level design and performance.