REDUCTION OF LEAKAGE POWER IN CMOS MUX USING LEAKAGE CONTROL TRANSISTOR IN 90nm TECHNOLOGY

The scaling down of technology results in scaling of threshold voltage thereby increasing the sub-threshold leakage current. Lector is a technique for designing CMOS circuits in which two leakage control transistors are introduced between PUN and PDN to reduce the leakage current without affecting the dynamic power dissipation, which made Lector a better technique in leakage power reduction when compared to all other existing leakage reduction techniques. This paper presents the analysis of leakage current in MUX using Lector technique by 90nm technology.