GEEP: A LOW POWER GENETIC ALGORITHM LAYOUT SYSTEM

In this paper we present GEEP, a genetic algorithm for low power standard-cell placement. GEEP reduces interconnect capacitance by an average of 20% over recursive min-cut area optimizing placement. It incorporates a number of heuristics to produce good placements fast relative to existing GAS, including a novel method for handling low population diversity. We tested GEEP on a suite of MCNC benchmarks and found this hybrid approach successful in producing good post-placement results in a reasonable number of generations. 1. MOTIVATION For the last twenty years, digital systems research has focused on increasing performance. The results of these efforts are substantial. Present-day technology operates many orders of magnitude faster than it did only a decade ago, while using dramatically less physical space. This trend has made digital devices fast, small, and relatively inexpensive. The ultimate outcome of this “digital revolution* is that computing devices are omnipresent in modern society. This technological change has made possible notebook computers and personal digital assistants (PDAs), which are expected to gain 32% of the personal computer market share by the year 1996 [Sin94]. It has been this explosive growth in portable computing that has spawned the majority of current low-energy VLSI research. Users of these machines refuse to sacrifice performance for extended battery life, which implies that marketwise developers must discover novel methods for minimizing energy consumption or lose competitive advantage in this rapidly expanding field. Drastic improvements in battery technology do not appear forthcomin - 30% growth over the next five years has been estimated bSB92, so efforts targeting energy must come from within the V !L SI CAD community.