Novel power transistor design for a process independent high voltage option in standard CMOS

High voltage transistors can be implemented in standard CMOS by interleaving drain extensions with STI using the fine STI/active patterns. This approach facilitates integration of high voltage transistors in modern processes without increasing processing complexity. This paper presents an in depth analysis of simulation and experimental data in a commercial 90 nm CMOS process. It is shown that the STI layout in the channel and the drain extension can be optimised separately which results in a better current drive of the resulting voltage transistors. The scope and limits of this device concept are discussed.