Multiple-precision subword-parallel multiplier using correction-value merging technique

This paper presents a 64-bit subword-parallel multiplier capable of supporting multiple precisions. The proposed multiplier uses novel correction-value merging technique to perform one 64times64, two 32times32 or four 16times16 bit unsigned/signed multiplication operations in parallel. The multiplier is implemented in 0.18 mum CMOS process. Critical path delay is 2.88 ns and layout area is 1.65 mm 2 , which are comparable to conventional multipliers.