A Quasi-Synchronous Sampling Energy Metering Chip with a Dedicated Dual-Core DSP

To enable harmonic analysis in smart meters, we design an energy metering chip that supports the quasi-synchronous sampling. The quasi-synchronous sampling is realized by the Newton polynomial interpolation algorithm. To implement the overall metering algorithm, we design a dedicated dual-core digital signal processor (DSP) with a primary core and a secondary core sharing the same data memory and arithmetic logic unit (ALU). The DSP also has a special data memory architecture with a dynamic shifting and virtual address mechanism, which simplifies the control in the DSP program. The quasi-synchronous sampling technique can achieve an accuracy of 0.3% in harmonic metering, meeting the requirement of single-phase smart meters.