CMOS latch metastability characterization at the 65-nm-technology node

A new test structure utilizing a differential technique for measuring CMOS latch delay with sub-ps time resolution is described. The latch delay and error count in the metastability region are measured as a function of clock-data delay which can be incremented in 0.1 ps steps. This compact test structure is configured to be placed in the scribe line for characterizing different latch designs and correlating their behavior with model predictions.