LOW POWER ADIABATIC PROGRAMMABLE LOGIC ARRAY WITH SINGLE CLOCK IAPDL

A novel implementation of a low power adiabatic PLA with a single power clock (IAPDL-SC PLA) is presented. The isolation transistor in the AND array is removed. The power clock is shared by the AND array and the OR array. In this way, the proposed PLA not only saves the device components but also reduces the power consumption. For 3 V VDD and 200 MHz power clock frequency, the simulation results using Hspice show that the power saving is 79.48% compared to dynamic CMOS PLA, 69.34% compared to APDL PLA, and 40.40% compared to IAPDL PLA. For the 5 × 8 × 4 PLA design, the device saving is 30.77% compared to APDL PLA and 12.90% compared to IAPDL PLA. The diodes are the critical components for all the technology designs. Current simulation is based on 0.8 μm process and the power consumption can be further reduced using the more downsized technology designs.