ATM over SDH: design of a STM-16c transceiver using GaAs technology

This article describes an ATM transceiver implementation with add/drop function over Synchronous Digital Hierarchy (SDH) able to handle STM-16c (OC-48c) signals. The design has been developed using Vitesse HGaAs-IV technology using Direct Coupled FET Logic (DCFL) standard cells and obtaining, in this way, a logic gate level description which could be easily exportable to any technology.