Design of SRAM array using reversible logic for an efficient SoC design

Recently, the power dissipation has become the prime concern with the system-on-chip (SOC) as technology scales. Further, the memory component of the design is as crucial, as it is energy consuming. The conventional approach of circuit designing consumes a lot of power and occupies much area. Thus, the concept of reversible logic in circuit designing is garnering growing attention for low-power applications such as DNA computing, quantum computing and ultra-low power CMOS design. This paper proposes a reversible design of 4-bit 6-T SRAM array at 180nm-1.8V CMOS technology which achieves 8% reduction in energy consumption of the circuit. The designs are simulated on Cadence virtuoso 6.1.4 schematic editor. The present work also concludes with some insights on the operation of conventional SRAM 6-T cell and the feasibility of reversible logic.