A review of III–V planar nanowire arrays: selective lateral VLS epitaxy and 3D transistors

Nanowires have long been regarded as a promising architecture for beyond Si CMOS logic, future III–V RF electronics, next generation optoelectronic applications, as well as heterogeneous integration. The inherent 3D structure also enables new device concepts that are otherwise not accessible with conventional technology. Nanowires grown using bottom-up epitaxial methods such as metalorganic chemical vapor deposition are free of ion-induced damage, which is especially critical for III–V because of the irreversibility of such damage, and can be scaled to dimensions smaller than lithographically defined. The challenges for nanowire based devices have been the controllability and compatibility with Si CMOS manufacturing. The discovery of parallel arrays of planar III–V nanowire growth mode provides an in-plane nanowire configuration that is perfectly compatible with existing planar processing technology for industry. The selective lateral epitaxy nature guided by the metal nanoparticles via the vapor–liquid–solid (VLS) mechanism opens up a new paradigm of crystal growth and consequently enabled in situ lateral and radial junctions. In this article, we review the planar nanowire based transistor development, particularly, planar III-As compound semiconductor based transistors enabled by this bottom-up self-assembled selective lateral VLS mechanism. We first review the characteristics and mechanism of planar nanowire growth, then focus on the growth, fabrication, and DC and RF performance of metal-semiconductor field-effect transistors, metal-oxide semiconductor field-effect transistors, and high electron mobility transistors (HEMTs), before providing our perspective on future development.