Experimental investigation of the embedded microchannel manifold cooling for power chips

Power chips with high power dissipation and high heat flux have caused serious thermal management problems. Traditional indirect cooling technologies could not satisfy the increasing heat dissipation requirements. The embedded cooling directly inside the chip is the hot spot of the current research, which bears greater cooling potential comparatively, due to the shortened heat transfer path and decreased thermal resistance. In this study, the thermal behaviors of the power chips were demonstrated using a thermal test chip (TTC), which was etched with microchannels on its substrate’s backside and bonded with a manifold which also fabricated with silicon wafer. The chip has normal thermal test function and embedded cooling function at the same time, and its size is 7 × 7 × 1.125 mm3. This paper mainly discussed the influence of width of microchannels and the number of manifold channels on the thermal and hydraulic performance of the embedded cooling structure in the single-phase regime. Compared with the conventional straight microchannel structure, the cooling coefficient of performance (COP) of the 8×-50(number of manifold distribution channels: 8, microchannel width: 50 μm)structure is 3.38 times higher. It’s verified that the 8×-50 structure is capable of removing power dissipation of 300 W (heat flux: 1200 W/cm2) at a maximum junction temperature of 69.6 ℃ with pressure drop of less than90.8 kPa. This study is beneficial to promote the embedded cooling research, which could enable the further release of the power chips performance limited by the dissipated heat.