Area Efficient High Speed Architecture of Bruun's FFT for Software Defined Radio

Fast Fourier Transform (FFT) is one of the most basic and essential operation performed in software defined radio (SDR). Therefore designing a universal, reconfigurable FFT computation block with low area, delay and power requirement is very important. Recently it is shown that Bruun's FFT is ideally suited for SDR even when operating with higher bit precision to maintain same NSR. In this paper, authors have proposed a new architecture for Bruun's FFT using a distributed approach for incrementing the number of bits (precision) with successive stages of FFT. It is also shown that proposed architecture further reduces the hardware requirement of Bruun's FFT with negligible changes in it's NSR. The proposed design makes Bruun's FFT, a better option for most practical cases in SDR. A detailed comparison of Bruun's traditional and proposed hardware architectures for same NSR is carried out and results of FPGA and ASIC implementations are provided and discussed.