Innovative practices on memory test practice

In this IP session, there will be 3 presentations focusing on the state-of-the-art memory test practices from tools and industrial implementation perspectives. The 1 st presentation will discuss the memory test strategies in the automotive space. The 2 nd presentation discusses memory tests strategies for enabling test cost reduction. The 3 rd presentation will discuss on array BIST and its presence and usage in various applications of the current generation designs.