Advances on NiPt SALICIDE process optimization for 28nm CMOS manufacturing

A NiPt silicide for CMOS ohmic contact formation process extension from 45nm to 28nm node has been achieved through co-optimization of NiPt alloy deposition thickness, Pt additive amount and complementarty wet selective etch process. In this study, it was found thicker NiPt film will lead to lower sheet resistance (Rs)but will reach saturation; meanwhile, will increase NiSi encroachment. To increase Pt additive will significantly retard NiSi encroachment behavior, but also increase difficulity of wet selective etch process that followed. The co-optimization has achieved with linear programming of NiPt film, Pt additive and complemented by new wet etch processor.