On-Chip Carbon Nanotube Interconnects: Adaptation to Multi-gate Transistors

Technology scaling into the nanometer regime has forced the research community to revisit the choice of on-chip interconnect materials. Copper, which is a traditional material for interconnects, has started encountering several limitations in giga-scale integration. Carbon nanotube (CNT) interconnects have emerged as one of the promising candidates for future on-chip interconnect technology to sustain the performance and reliability of nanoscaled integrated circuits. The overall signal integrity not only depends on interconnect but also on the quality of drivers and repeaters, which may be designed with the help of multi-gate transistors (MGTs). The on-resistance and capacitance offered by MGTs are quite different from their conventional planar counterparts. This, along with the inherent variability in MGTs, which may be induced as a result of fabrication imperfections, impose challenges in adapting interconnects to such transistors. After presenting some electrical properties and modeling approaches of CNTs, this chapter is an effort to familiarize the reader with the various effects of using MGT-based driver circuits using gate-all-around (GAA) devices. Methods for improving interconnect delay using GAA devices in presence of device variability have also been presented.