An Introduction to Universal Verification Methodology for the digital design of Integrated circuits (IC’s): A Review

System on chip (SOC) Verification is very important for difficulty in the digital design of Integrated circuits (IC’s) which results in demanding logic or functional verification in terms of verification platform complexity with goals like code coverage, functional coverage and boundless verification time of the given digital designs. After analyzing the role of Universal Verification methodology (UVM) during the verification, this paper carries out the literature survey and the case study of UVM in functional Verification and architecture of UVM for system verification is carried out. The UVM consists of rich base class library and also provides a best reference for the practice of verification methodology. The UVM is the verification standard for verification of digital system by coverage driven verification approach. It provides a framework to create structured test environment, providing the reusability of verification components and scenarios.