Improving code efficiency for reconfigurable VLIW processors
2002
High code efficiency (operations per instruction) combined with a high degree of instruction level parallelism can rarely be obtained by hardwired microprocessor designs for a broad application domain. The implementation of reconfigurable execution units is a promising way to enhance code efficiency and microprocessor performance. However, the unit reconfiguration process introduces an additional dimension to the code generation phase, which complicates scheduling and may lead to code deficiencies if resource conflicts occure. This paper discusses code generation issues for a runtime-reconfigurable VLIW processor model, which combines fixed and flexible functional units (FU) in one template. Reconfigurable units (RFU) can be adapted to the application demands exploiting more coarse-grain parallelism than common instruction-level FUs. A case study illustrates the extraction of conditions for reconfigurable instructions proves scheduling possibilities for a set of common DSP benchmark algorithms. The software environment described includes a retargetable, parallelizing C compiler based on the SUIF compiler kit and a simulator, which can be used for identifying application-specific SIMD-instruction candidates and for evaluating the runtime behavior of the created object code.
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