A Novel high-speed transistorized 8x8 Multiplier using 4-2 Compressors

In this paper, a novel implementation of 8x8 Multiplier using 4-2 Compressors is presented; which produces quick results, especially for use in Digital Signal Processors and in Microprocessors. This multiplier uses a new partial-product reduction format which consecutively reduces the maximum output delay. The new design of multiplier requires less number of MOSFET's compared to Wallace Tree Multipliers. The 4-2 Compressor used is made from high-speed and low-power XOR-XNOR module and transmission gate based Multiplexer. The delay and power-delay product (PDP) is compared with earlier Wallace and Dadda Multipliers, implemented with 4-2 Compressors and without compressors, and is proven to have minimum delay and PDP. The Simulation results were obtained using HSPICE at 0.18µm standard CMOS technology.