Old Web
English
Sign In
Acemap
>
Paper
>
Process Engineering and Trap Distribution for Dielectric/Si Interfacial Layer in High-k Gated MOS Devices
Process Engineering and Trap Distribution for Dielectric/Si Interfacial Layer in High-k Gated MOS Devices
2011
Kuei-Shu Chang-Liao
Chung-Hao Fu
Chun-Chang Lu
Yu-An Chang
Ya-Yin Hsu
Che-Hao Tsao
Tien-Ko Wang
Dawei Heh
Yu-Chen Li
Wen-Fa Tsai
Chi-Fong Ai
Fu-Chung Hou
Yao-Tung Hsu
Keywords:
Dielectric
High-κ dielectric
Analytical chemistry
Materials science
Engineering physics
Correction
Source
Cite
Save
Machine Reading By IdeaReader
0
References
2
Citations
NaN
KQI
[]